Name

forge - an FPGA toolchain you can read

Synopsis

Description

forge is a native FPGA flow: synthesis, technology mapping, static timing, placement, routing, and configuration images in one tool, no license server attached. SystemVerilog in, deterministic bitstreams out.

Builds are deterministic: same input, same bytes, any machine. Today it implements its own generic fabric end to end; broader device support is in progress. The source drops when it's ready.

Examples

$ forge hdl implement --top top --clock-period 5ns rtl/top.sv
[INFO] Synthesis clean. Netlist mapped to LUTs, carry, BRAM.
[STAGE] Placed and routed. 0 overused edges. Setup WNS +4520 ps.
[FORGE] design.fgb written. Run it again: byte-identical.

Source

Commit 8a1f9dd. Release pending.

See Also

dqc(7), nsh(8)